An MTJ memory device comprises three basic layers, a free ferromagnetic layer, an insulating tunneling barrier, and a pinned ferromagnetic layer. The magnetization moments of the free ferromagnetic layer are free to rotate under an external magnetic field. The pinned ferromagnetic layer can comprise a ferromagnetic layer and/or an anti-ferromagnetic layer that pins the magnetic moments in the ferromagnetic layer. Thus, the magnetization moment of the pinned ferromagnetic layer is pinned in a fixed direction. A very thin insulation layer forms the tunneling barrier between the pinned and free ferromagnetic layers.
The MTJ memory device can be electrically represented as a resistor. The size of the resistance depends upon the orientation of the magnetization of the free ferromagnetic layer and the pinned ferromagnetic layer. As is understood by those skilled in the art, the MTJ memory device has a relatively high resistance when the magnetic vectors are misaligned (point in opposite directions) and a relatively low resistance when the magnetic vectors are aligned. That is, an MTJ memory device stores a bit of information as the relative orientation of the magnetizations of the free ferromagnetic layer and the pinned ferromagnetic layer. In other words, the magnetization of each MTJ memory device at any given time assumes one of two stable orientations. These two stable orientations, referred to as “parallel” and “anti-parallel” magnetic orientation, represent logic values of “0” and “1”, for example.
To write or change the state in a basic MTJ memory device, an external magnetic field can be applied that is sufficient to completely switch the stable orientation of the magnetization of the free ferromagnetic layer. To sense states in the MTJ memory device, a read current can be applied through the MTJ memory device. As the magneto-resistance varies according to the state stored in the MTJ memory device, the logic state of the MTJ memory device can be sensed by obtaining the voltage difference across the MTJ memory device. An MRAM array comprises a plurality of MTJ memory devices, and the binary logic data of entire MRAM array is typically read by applying a sensing current flowing perpendicularly through selected MTJ memory device. Switches, typically transistors like MOSFETs, are implemented in conventional methods to block the stray read current path. In addition, the switches are also used to avoid write disturbance.
Some MRAM circuit arrays employ one transistor for each bit (each memory cell or bit is thus noted as 1T1R) to control the read current and block the sneak current paths. This type of MRAM array typically offers fast memory speeds, such as used in L1 cache memory. However, the one-to-one ratio of switches to MTJ stacks in such arrays limits array density. Other array layouts employ two transistors for each MTJ stack (noted as 2T1R). However, although this design provides very fast speeds, such designs provide insufficient cell density due to the relatively large area occupied by the switching devices in relation to MTJ stacks. Still other array layouts employ one transistor for two or more MTJ stacks (noted as 1T2R, or 1TnR for “n” number of MTJ stacks per switching device). However, while these layouts provide for increased MRAM cell density per chip real estate, they typically lack the desired fast access speeds demanded in today's market. As can be seen, available MRAM array layouts result in a give-and-take for various applications. Accordingly, a new type of array layout for memory cell arrays such as MRAM devices is needed.